The demand for higher capacity semiconductor memory devices has resulted in improved techniques to form memory devices and structures therein at higher levels of integration. However, because higher levels of integration typically require memory devices having smaller unit cell size, the area occupied by a cell capacitor in a memory device, such as a DRAM device, may have to be reduced significantly. As will be understood by those skilled in the art, this reduction in cell capacitor area can degrade memory cell performance at low voltages and adversely impact soft-error rate (SER) caused by .alpha.-particle radiation.
Conventional methods of increasing cell capacitor surface area include forming cell capacitor electrodes (e.g., storage electrodes) with hemispherical grain (HSG) silicon surface layers. For example, a conventional method of forming HSG silicon surface layers on cell capacitor electrodes is disclosed in U.S. Pat. No. 5,407,534 to Thakur. However, while capacitors having HSG surface layers therein have manifested enhanced capacitance in high density integrated circuits, HSG capacitors may lack stability and may incur performance degradation over the lifetime of an integrated circuit memory device. Other methods of increasing cell capacitor area include the use of trench-based capacitor electrodes. Unfortunately, the processing techniques typically used to form these types of electrodes are complex.
Thus, notwithstanding the above-described methods, there continues to be a need for improved methods of forming integrated circuit capacitors.